Method for manufacturing semiconductor package

ABSTRACT

Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip.

CROSS REFERENCE TO RELATED APPLICATION

This application is a Continuation of U.S. patent application Ser. No.14/527,733, filed Oct. 29, 2014, which claims the benefit of KoreanPatent Application No. 10-2013-0143761, filed on Nov. 25, 2013, entitled“Method For Manufacturing Semiconductor Package”, which is herebyincorporated by reference in its entirety into this application.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a method for manufacturing asemiconductor package.

2. Description of the Related Art

To cope with the increase in demand for light, small, high-speed,multi-functional, and high-performance electronic products, a technologyof packaging a semiconductor chip has been developed.

Generally, a semiconductor package is manufactured by first cutting awafer along a scribe line to be separated into individual semiconductorchips and packaging the individual semiconductor chips.

Recently, a method for manufacturing the package by performing apackaging process in the wafer state without first cutting the wafer andthen finally cutting the wafer along the scribe line has been proposed.

A wafer level package (WLP) or a semiconductor chip scale package (CSP)has been developed to provide another solution for a directly attachedflip chip device.

A wafer level package (WLP) technology is a technology of implementingminiaturization, weight reduction, high performance, and the like.

An embedded type of wafer level package enables a manufacturing of thewafer level package having a fan-out form in which an externalconnection terminal may be disposed in a package larger than a size ofthe semiconductor chip.

PRIOR ART DOCUMENT Patent Document

(Patent Document 1) International Patent Laid-Open Publication No. WO2009-035858

SUMMARY OF THE INVENTION

The present invention has been made in an effort to provide a method forimproving pattern alignment and EMC molding flatness based on an epoxymolding compound (EMC) molding technology which enables a fan out waferlevel package (fan out WLP) to have a substrate size to therebymass-produce the fan out WLP.

Further, the present invention has been made in an effort to provide amethod for encapsulating a plurality of semiconductor devices alreadyseparated and then separating the semiconductor devices into individualchips in a final process.

According to a preferred embodiment of the present invention, there isprovided a method for manufacturing a semiconductor package, including:preparing a rectangular frame having a plurality of quadrangular holes;attaching a plurality of semiconductor chips and the frame on onesurface of a tape; forming a molding part on the tape to cover thesemiconductor chip and the frame; peeling the tape; forming a resinlayer at a portion at which the tape is peeled; and forming a wiring onthe resin layer to be connected to the semiconductor chip.

The method for manufacturing a semiconductor package may furtherinclude: prior to the peeling of the tape, curing the molding part.

The resin layer may be formed in a single layer or a multilayer.

The frame may be an epoxy molding compound (EMC).

In the attaching of the plurality of semiconductor chips and the frameon one surface of a tape, the semiconductor chips may be spaced fromeach other and thus may be attached within the quadrangular holes of theframe in a face-down type.

A cross section height of the frame may be larger than a thickness ofthe semiconductor chip.

The molding part may be an epoxy molding compound (EMC).

The method for manufacturing a semiconductor package may furtherinclude: after the forming of the molding part, curing the molding partto fix the semiconductor chip.

The frame and the molding part may have different colors.

The forming of the wiring may include: forming a via hole in the resinlayer; and forming the wiring by plating and filling the via hole.

The method for manufacturing a semiconductor package may furtherinclude: after the forming of the wiring, forming a solder ball, whichis an external connection terminal part, on the wiring.

The method for manufacturing a semiconductor package may furtherinclude: after the forming of the wiring, singulating the semiconductorpackage as individual semiconductor packages by a sawing process,wherein in the singulating of the semiconductor package, a dummy partbetween the frame and the individual semiconductor package is removed.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will be more clearly understood from the following detaileddescription taken in conjunction with the accompanying drawings, inwhich:

FIGS. 1 to 8 are process diagrams sequentially illustrating a method formanufacturing a semiconductor package according to a preferredembodiment of the present invention, in which

FIG. 1 is a front view and FIGS. 2 to 8 are cross-sectional views.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The objects, features and advantages of the present invention will bemore clearly understood from the following detailed description of thepreferred embodiments taken in conjunction with the accompanyingdrawings. Throughout the accompanying drawings, the same referencenumerals are used to designate the same or similar components, andredundant descriptions thereof are omitted. Further, in the followingdescription, the terms “first”, “second”, “one side”, “the other side”and the like are used to differentiate a certain component from othercomponents, but the configuration of such components should not beconstrued to be limited by the terms. Further, in the description of thepresent invention, when it is determined that the detailed descriptionof the related art would obscure the gist of the present invention, thedescription thereof will be omitted.

Hereinafter, preferred embodiments of the present invention will bedescribed in detail with reference to the attached drawings.

Method For Manufacturing Semiconductor Package

FIGS. 1 to 8 are process diagrams sequentially illustrating a method formanufacturing a semiconductor package 100 according to a preferredembodiment of the present invention, in which FIG. 1 is a front view andFIGS. 2 to 8 are cross-sectional views.

Referring first to FIG. 1, FIG. 1 is a front view of a frame of thesemiconductor package according to a preferred embodiment of the presentinvention.

A quadrangular frame 10 having a plurality of quadrangular holes isprepared.

In this case, the frame 10 may be manufactured at various sizes so as toeasily mass-produced and may be used.

Further, the plurality of quadrangular holes may be manufactured at aproper size, and thus may be inserted with semiconductor chips 30 to bedescribed below and a size of the quadrangular holes may also be changeddepending on a size of the semiconductor chip 30.

In addition, the frame 10 according to the preferred embodiment of thepresent invention may be represented by a color different from a moldingpart 40 to easily be differentiated from the molding part 40 to bedescribed below.

Herein, a material of the frame 10 may be an epoxy molding compound(EMC). However, according to the preferred embodiment of the presentinvention, the material of the frame is not limited thereto, andtherefore any material to facilitate cutting in a sawing process may beused.

As described above, according to the method for manufacturing a waferlevel semiconductor package, the cutting of the wafer levelsemiconductor package may be facilitated by using the above materialwhen the semiconductor substrate is manufactured at a larger area likethe general substrate, not at the existing wafer level size and then isfinally singulated.

Further, when as the material of the frame 10, metal, ceramics, and acomposite material thereof having high strength and excellent durabilityare used, characteristics of the frame 10 supporting the semiconductorchip 30 may be improved.

In addition, when a mark is formed in the frame 10 to improve thealignment of the semiconductor package 100, the semiconductor package100 may suffer from segmentation correction and manufacturingcompleteness thereof may be increased.

Next, referring to FIGS. 2 and 3, the plurality of semiconductor chips30 and the frame 20 are attached on one surface of a tape 20.

The frame 10 and the semiconductor chips 30 are bonded on the onesurface of the tape 20 by preparing the film-shaped tape 20 having apredetermined level of adhesion.

In this case, a cross section height of the frame 10 may be higher thanthat of the semiconductor chip 30.

Further, a thickness of the cross section of the frame 10 may becontrolled as the designer demand.

In this case, the frame 10 formed with the mark is first bonded and thenthe semiconductor chip 30 is bonded, such that the frame 10 may beaccurately bonded at positions at which the individual semiconductorchips 30 are bonded.

Herein, a connection pad of the semiconductor chip 30 is bonded with thetape 20 by a face-down type.

This is a manufacturing method to facilitate the manufacturing of thewafer level semiconductor package in a fan-out form, in which theconnection pad of the semiconductor chip 30 bonded with the tape 20 isconnected to a solder ball 70, which is an external connection terminalpart, by a wiring 61 to be described below.

The above drawings do not illustrate in detail components of thesemiconductor chip 30 and therefore schematically illustrate thecomponents, but a person having ordinary skill in the art to which thepresent invention pertains may sufficiently recognize that thesemiconductor chip 30 having all the known structures may be applied tothe present invention without being particularly limited.

Next, referring to FIG. 4, the molding part 40 is formed on the tape 20to cover the semiconductor chip 30 and the frame 10.

The molding part 40 is formed to be filled on the tape 20, and themolding part 40 is formed and then cured such that the semiconductorchip 30 may be well fixed.

Further, thermal insulation of the semiconductor chip 30 is effectivelyperformed by forming the molding part 40.

In this case, as the material of the molding part 40, a silicon gel, anepoxy molding compound (EMC), and the like, may be used, but thepreferred embodiment of the present invention is not limited thereto.

Next, retelling to FIGS. 5 and 7, the tape 20 is peeled and then aportion from which the tape 20 is removed is provided with a resin layer50.

In this case, the resin layer 50 may be formed in a single layer or amultilayer.

Herein, as a material of the resin layer 50, a photosensitive insulatingmaterial or a resin insulating layer may be used.

As a material of the resin insulating layer, a thermo-setting resin suchas an epoxy resin, a thermo-plastic resin such as a polyimide resin, aresin having a reinforcement material such as a glass fiber or aninorganic filler impregnated in the thermo-setting resin and thethermo-plastic resin, for example, a prepreg may be used. In addition, athermo-setting resin, a photo-curable resin, and the like, may be used.However, the material of the resin insulating layer is not particularlylimited thereto.

Further, the formed resin layer 50 is formed with a via hole 60 so as toexpose the connection pad of the semiconductor chip 30 and then isprovided with the wiring 61 to be connected to the outside.

In this case, the wiring 61 is formed by forming the via hole 60 in theresin layer 50 and then plating and filling the via hole 60.

Herein, the method for forming a via hole 60 may be formed by beingexposed and developed and may be formed by laser machining.

In this case, the laser machining preferably uses a CO2 laser, but inthe preferred embodiment of the present invention, a kind of laser isnot particularly limited.

Herein, the wiring 61 may be formed by plating and filling an inner wallof the via hole 60 with an insulating material by electroless platingand electroplating which are a general plating method.

Next, the solder ball which is the external connection terminal part isformed on the wiring 61.

Since the solder ball 70 is fixed by reflow but the contact reliabilityof solder tends to be reduced, some of the solder balls are buried inthe insulating layer to strengthen a fixing force of the solder balls 70and the rest thereof is exposed to the outside, thereby improving thereliability.

Finally, referring to FIG. 8, the semiconductor package is singulated asthe individual semiconductor package 100 by the sawing process.

The semiconductor package 100 is formed by cutting the individualsemiconductor chips 30 attached with the solder balls 70 by theconnection with the wirings 61 based on the frame 10.

Herein, a dummy part between the frame 10 and the individualsemiconductor package 100 is removed. In this case, the mark formed onthe frame 10 and the material of the frame 10 are easy for the cutting.

Further, when the frame 10 is made of the epoxy molding compound (EMC),the frame 10 may be used without causing any problem in reliability evenin the case in which the frame 10 is included in the unit semiconductorpackage 100.

Therefore, the individually formed semiconductor package 100 may also bemade of a part of the frame 10 and the molding part 40 depending on theseparation method and may be made of only the molding part 40.

According to the method for manufacturing a semiconductor package 100according to the preferred embodiments of the present invention, it ispossible to minimize the defect of products which may occur due to thehandling problem at the time of performing the process by using theframe 10 serving as the supporter.

Further, according to the preferred embodiments of the presentinvention, it is possible to make the alignment between thesemiconductor chips 30 excellent at the time of manufacturing thesemiconductor package using the frame 10 formed with the mark used inthe method for manufacturing a semiconductor package 100.

In addition, it is possible to efficiently mass-produce thesemiconductor package by molding a large number of semiconductor chips30 to have a larger area than that of the existing wafer levelsemiconductor package.

Moreover, since the frame 10 is made of the material similar to that ofthe molding part 40, the reliability of products is not affected evenwhen the cut portion is not accurately removed at the time of performingthe sawing process, such that the defects may be minimized and themanufacturing costs may be reduced.

Although the embodiments of the present invention have been disclosedfor illustrative purposes, it will be appreciated that the presentinvention is not limited thereto, and those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the invention.

Accordingly, any and all modifications, variations or equivalentarrangements should be considered to be within the scope of theinvention, and the detailed scope of the invention will be disclosed bythe accompanying claims.

1. A method for manufacturing a package, comprising: preparing a framehaving holes; disposing an element in a hole of the frame; forming amolding part to cover the element; forming a redistribution layer (RDL)on one side of the frame and the element. 2-5. (canceled)
 6. The methodof claim 1, wherein a thickness of the frame is greater than a thicknessof the element.
 7. The method of claim 1, wherein the molding part is anepoxy molding compound (EMC).
 8. (canceled)
 9. The method of claim 1,wherein the frame and the molding part have different colors.
 10. Themethod claim 1, wherein the forming of the RDL comprises: forming aninsulating layer; forming a via hole in the insulating layer; andforming the wiring by plating and filling the via hole.
 11. The methodof claim 10, further comprising: after the forming of the wiring,forming a connecting terminal, which is an external connection terminalpart, on the wiring.
 12. (canceled)
 13. The method of claim 1, whereinthe disposing the element in the hole of the frame comprises: attachinga portion of adhesive tape to one surface of the frame; and attachingthe element to a portion of the adhesive tape exposed by the hole of theframe.
 14. The method of claim 13, further comprising: after the formingof the molding part, peeling the tape.
 15. A method for manufacturing apackage, comprising: preparing a frame having a plurality of holes;disposing a plurality of elements in the holes of the frame,respectively; forming a molding part to cover the elements; forming aredistribution layer (RDL) on one side of the frame and the elements;and singulating the package as a plurality of individual unit packages.16. The method of claim 15, wherein after the singulating of thepackage, at least a portion of the frame remains on side surfaces of theindividual unit packages.
 17. The method of claim 15, wherein after thesingulating of the package, the frame is removed in the individual unitpackages.